Clockport Splitter
About
How It Works
Schematics
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How a Clock Port Works
The clockport was only designed for handling a simple real-time clock board, so it didn't need full access to all the Amiga's buses. So, the hardware designers gave it 8 of the machine's 32 data bus bits, and 4 of the machines addresss lines. It also includes some other control lines - Chip Select, Interrupt 6, read and write signals, reset, and +5V for power. The Chip Select used to enable the clock port is decoded to $D80000 in the Amiga's 24-bit custom chip space, meaning some 64KB of space is reserved for any peripheral connected. However, seeing as there are only 4 address lines (A2, A3, A4 and A5) available, this limits the port to 16 byte addresses, in 4-byte steps due to A0 and A1 being missing. These addressses are as follows:
| $D80001
| $D80005
| $D80009
| $D8000D
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| $D80011
| $D80015
| $D80019
| $D8001D
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| $D80021
| $D80025
| $D80029
| $D8002D
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| $D80031
| $D80035
| $D80039
| $D8003D
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(All addressses are odd due to the CPU writing data in 16-bit words, and only data bits 16-23 being available at the clock port.)
So all clock port peripherals have been designed with this 16-byte data transfer scheme, ignoring the bus altogether when disabled via the Chip Select signal. However, there's a lot of empty space left between $D8003D and $D8FFFF, which is the top of the allocated area for the clock port. If the middle byte (which is totally unused) could be somehow used to address different clockports, the original data transfer method used by all the peripheral drivers so far could remain unchanged; drivers would only have to mask off the appropriate value in the second address byte to transfer to their peripheral as if it were the only device connected. Simple really!
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The Workings of the Clockport Splitter
Since I didn't write the drivers for any of the clockport add-ons out there, I asked Jens Schoenfeld himself how he had implemented this in his drivers, nad he told me that his drivers were able to address a total of 4 different clock ports: one at $D80000 (the original address) and three at 16KB intervals to split the allocated 64KB of address space evenly between the ports. So, to select a port in 16KB intervals (that is, addresses $D80000, $D84000, $D88000 and $D8C000), address lines A14 and A15 are required. But these of course aren't available at the clock port so must be brought in from somewhere else. I considered the A1200's trapdoor connector as this has all the bus signals on it, but having an accelerator there made it awkward. In the end, to avoid messy patching onto some solder pads on the mainboard, I added a DIL socket to U6B (under one of the ROM chips, as these sockets both had the address lines required) and ran wires from that for A14 and A15. These two address lines were sent to the inputs of one half of a 74LS139, which is a 1-to-4 decoder with an inhibit input. This chip's output gave me four individual enable lines - one for the Chip Select of each new clock port, and the inhibit input was connected tothe original port's Chip Select to disable or enable the decoded output as required. A very neat solution indeed!
The schematics I've dug out are very old, and PLEASE BE CAREFUL! According to Ian Stedman's website, my pin numbering may seem confusing, with my pin 1 corresponding to the original pin 40, and my pin 22 corresponding the original pin 19 of a fully intact, 40-pin clock port. However, there was never a formal convention for using the clockport like this, and some manufacturers (e.g. Individual Computers) treat pin 40 as pin 1. Since the The clock port's a dangerous thing, do your own research if you're unsure of the pinouts! Anyway, in the end I only ever built this on the back of a DIL socket and only ever tried and used the first two ports, I don't see why all 4 shouldn't work, and why it can't be put on a PCB. I even did a quick routing in AmiPCB which I've included with the schematic, but I don't think it'll be of much use to anyone.
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Credit Where Credit's Due
This wasn't entirely my own design of course - at the time I knew far less about the clock port than I do now, and I couldn't have built it without the help and guidance of Jens Schoenfeld and Ian Stedman. Thanks guys! I learned a lot about my Amiga through this project! Also, I'm sure there are others who helped me in the IRC channel #AmiHelp and on the Amiga-Hacks mailing list. Thanks to you too, you know who you are even if I don't ;)
Disclaimer
Of course, anyone wanting to try this out does so at their own risk. It involves some very risky activity - connecting to unbuffered CPU buses is never totally safe. And there's an unprotected +5V available on the clock port, so it's EXTREMELY easy to fry a) your newly built circuit; b) your clock port cable; c) your Amiga's motherboard; d) any of those extremely expensive, delicate and rare accelerators, graphics cards and other peripherals you've added to your machine with love over the years. I'm just a guy on the internet, for all you know I could have just made this all up... I didn't though - trust me!
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